The present invention relates to a vector operation instruction issue control method for a vector processing apparatus and, more particularly, to a vector operation instruction issue control method for activating a vector operation instruction in a vector arithmetic unit including two arithmetic functions having different numbers of pipeline stages.
In a vector processing apparatus for successively supplying vector data held in a vector register to a vector arithmetic unit and executing a vector operation at high speed by so-called pipelining, a single arithmetic unit is conventionally allowed to have two arithmetic functions with different number of pipeline stages (to be referred to as simply stages hereinafter) and execute two types of operations.
FIGS. 4A to 4C are views for explaining an operation of such a vector arithmetic unit. In FIG. 4A, a vector arithmetic unit 40 has an arithmetic function with a large number of stages (e.g., five stages for the sake of simplicity of the following description) and that with a small number of stages (e.g., two stages for the sake of simplicity of the following description). Upon activation, the arithmetic unit 40 performs an arithmetic function of the externally designated type. Assume that a vector element number (VL) is "5" and that the vector arithmetic unit 40 is caused to execute a vector operation instruction using the arithmetic function of five stages (to be referred to as a long-stage vector operation instruction A hereinafter) and to execute a vector operation instruction using the arithmetic function of two stages (to be referred to as a short-stage vector operation instruction B hereinafter).
FIG. 4B is a schematic timing chart for explaining an operation executed when the long-stage vector operation instruction A is issued to the vector arithmetic unit 40. When the long-stage vector operation instruction A is issued, a first element el to a fifth element e5 of vector data held in vector registers 41 are successively supplied to the vector arithmetic unit 40. Each element passes through five stages S1 to S5 in the vector arithmetic unit 40 to perform a predetermined operation, and the result is stored in the vector registers 41 again. A time period from reading of the first to fifth elements e1 to e5 from the vector registers 41 to completion of inputting thereof in the vector arithmetic unit 40 corresponds to vector register reading (R), and that from reading of the first element el from the vector registers 41 to writing of an operation result of the fifth element e5 therein corresponds to vector register writing (W).
FIG. 4C is a schematic timing chart for explaining an operation executed when the short-stage vector operation instruction B is issued to the vector arithmetic unit 40. Assume that the short-stage vector operation instruction B is to be executed by using the first and fifth stages S1 and S5 of the above five stages S1 to S5. In this case, when the short-stage vector operation instruction B is issued, the vector data elements e1 to e5 successively supplied from the vector registers 41 to the vector arithmetic unit 40 pass through the first and fifth stages S1 and S5 to perform predetermined operations, and the results are stored in the vector registers 41 again. The period of the vector register reading (R) of the short-stage vector operation instruction B is the same as that of the long-stage vector operation instruction A, but the period of its vector register writing (W) is shorter than that of the long-stage vector operation instruction A because the number of stages is small.
As described above, in the vector arithmetic unit having the two arithmetic functions with different number of stages, the vector writing (W) period, i.e., a period during which data stays in the vector arithmetic unit 40 differs between execution of the long-stage vector operation instruction A and that of the short-stage vector operation instruction B. Therefore, in order to successively issue vector operation instructions, issue timings must be determined in consideration of the numbers of stages to be used by each two successive vector operation instructions. Such vector operation instruction issue timing control is conventionally performed as follows.
When vector operation instructions having the same number of stages are to be successively issued or when a preceding instruction is the short-stage vector operation instruction B and a subsequent instruction is the long-stage vector operation instruction A, immediately after the vector register reading (R) period of the preceding vector operation instruction has elapsed, the subsequent vector operation instruction is issued. For this purpose, a flag representing the vector register reading (R) is used to control issue of the subsequent vector operation instruction. FIGS. 5A, 5B and 5C are timing charts for explaining this control.
Assuming that the preceding instruction is the long-stage vector operation instruction A and the subsequent instruction is the short-stage vector operation instruction B, if issue is controlled by the above vector register reading flag, data to be processed by the preceding instruction overlaps that to be processed by the subsequent instruction in the vector arithmetic unit 40 as shown in FIG. 5D. Therefore, in a conventional method, a flag representing the vector register writing (W) is used to control issue of the subsequent short-stage vector operation instruction B.
As described above, in the conventional vector operation instruction issue control method, if a preceding instruction is the long-stage vector operation A and a subsequent instruction is the short-stage vector operation instruction B, issue of the subsequent short-stage vector operation instruction B is controlled by the vector register writing flag. Therefore, the subsequent short-stage vector operation instruction B is issued after an operation of the vector arithmetic unit 40 according to the long-stage vector operation instruction A is completely finished. For this reason, an unnecessary empty time is produced between the long- and short-stage vector operation instructions A and B.